The CMOD[1:0] bits may be read or written at any time. Disabling the TPM counter bywriting zero to the CMOD[1:0] bits does not affect the TPM counter value or otherregisters, but must be acknowledged by the TPM counter clock domain before they readas zero.The external clock input passes through a synchronizer clocked by the TPM counterclock to assure that counter transitions are properly aligned to counter clock transitions.Therefore, to meet Nyquist criteria considering also jitter, the frequency of the externalclock source must be less than half of the counter clock frequency.30.4.2 PrescalerThe selected counter clock source passes through a prescaler that is a 7-bit counter. Thevalue of the prescaler is selected by the PS[2:0] bits. The following figure shows anexample of the prescaler counter and TPM counter.0000 00 00 00 0 011 12 23 311 1 1 11 1 11selected input clockprescaler countertimer module counting is up.PS[2:0] = 001CNTIN = 0x0000timer module counterFigure 30-59. Example of the Prescaler Counter30.4.3 CounterThe TPM has a 16-bit counter that is used by the channels either for input or outputmodes. The counter updates from the selected clock divided by the prescaler.The TPM counter has these modes of operation:• up counting (see Up Counting)• up-down counting (see Up-Down Counting)30.4.3.1 Up CountingUp counting is selected when (CPWMS = 0)Functional DescriptionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012506 Freescale Semiconductor, Inc.
