28.3.3 ADC Configuration Register 2 (ADCx_CFG2)Configuration Register 2 (CFG2) selects the special high-speed configuration for veryhigh speed conversions and selects the long sample time duration during long samplemode.Address: 4003_B000h base + Ch offset = 4003_B00ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0MUXSELADACKENADHSCADLSTSWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADCx_CFG2 field descriptionsField Description31–8ReservedThis field is reserved.This read-only field is reserved and always has the value 0.7–5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4MUXSELADC Mux SelectChanges the ADC mux setting to select between alternate sets of ADC channels.0 ADxxa channels are selected.1 ADxxb channels are selected.3ADACKENAsynchronous Clock Output EnableEnables the asynchronous clock source and the clock source output regardless of the conversion andstatus of CFG1[ADICLK]. Based on MCU configuration, the asynchronous clock may be used by othermodules. See chip configuration information. Setting this field allows the clock to be used even while theADC is idle or operating from a different clock source. Also, latency of initiating a single or first-continuousconversion with the asynchronous clock selected is reduced because the ADACK clock is alreadyoperational.0 Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and aconversion is active.1 Asynchronous clock and clock output is enabled regardless of the state of the ADC.2ADHSCHigh-Speed ConfigurationTable continues on the next page...Chapter 28 Analog-to-Digital Converter (ADC)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 427
