In addition, there are two signals formed by the MTB_DWT module and driven to theMTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals canbe configured using the trace watchpoints to define programmable addresses and datavalues to affect the program trace recording state.19.3 Memory Map and Register DefinitionThe MTB_RAM and MTB_DWT modules each support a sparsely-populated 4 KBaddress space for their programming models. For each address space, there are a varietyof control and configurable registers near the base address, followed by a large unusedaddress space and finally a set of CoreSight registers to support dynamic determination ofthe debug configuration for the device.Accesses to the programming model follow standard ARM conventions. Taken from theARM CoreSight Micro Trace Buffer documentation, these are:• Do not attempt to access reserved or unused address locations. Attempting to accessthese locations can result in UNPREDICTABLE behavior.• The behavior of the MTB is UNPREDICTABLE if the registers with UNKNOWNreset values are not programmed prior to enabling trace.• Unless otherwise stated in the accompanying text:• Do not modify reserved register bits• Ignore reserved register bits on reads• All register bits are reset to a logic 0 by a system or power-on reset• Use only word size, 32-bit, transactions to access all registers19.3.1 MTB_RAM Memory MapMTB memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/pageF000_0000 MTB Position Register (MTB_POSITION) 32 R/W Undefined 19.31.1/273F000_0004 MTB Master Register (MTB_MASTER) 32 R/W See section 19.31.2/275F000_0008 MTB Flow Register (MTB_FLOW) 32 R/W Undefined 19.31.3/277F000_000C MTB Base Register (MTB_BASE) 32 R Undefined 19.31.4/279F000_0F00 Integration Mode Control Register (MTB_MODECTRL) 32 R 0000_0000h 19.31.5/279F000_0FA0 Claim TAG Set Register (MTB_TAGSET) 32 R 0000_0000h 19.31.6/280F000_0FA4 Claim TAG Clear Register (MTB_TAGCLEAR) 32 R 0000_0000h 19.31.7/280F000_0FB0 Lock Access Register (MTB_LOCKACCESS) 32 R 0000_0000h 19.31.8/281Table continues on the next page...Memory Map and Register DefinitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012272 Freescale Semiconductor, Inc.
