30.4.9 DMAThe channel generates a DMA transfer request according to DMA and CHnIE bits (seethe following table).Table 30-83. Channel DMA Transfer RequestDMA CHnIE Channel DMA Transfer Request Channel Interrupt0 0 The channel DMA transfer request is notgenerated.The channel interrupt is not generated.0 1 The channel DMA transfer request is notgenerated.The channel interrupt is generated if (CHnF = 1).1 0 The channel DMA transfer request is generated if(CHnF = 1).The channel interrupt is not generated.1 1 The channel DMA transfer request is generated if(CHnF = 1).The channel interrupt is generated if (CHnF = 1).If DMA = 1, the CHnF bit can be cleared either by channel DMA transfer done or writinga one to CHnF bit (see the following table).Table 30-84. Clear CHnF BitDMA How CHnF Bit Can Be Cleared0 CHnF bit is cleared by writing a 1 to CHnF bit.1 CHnF bit is cleared either when the channel DMA transfer is done or by writing a 1 to CHnF bit.30.4.10 Reset OverviewThe TPM is reset whenever any chip reset occurs.When the TPM exits from reset:• the TPM counter and the prescaler counter are zero and are stopped (CMOD[1:0] =0:0);• the timer overflow interrupt is zero;• the channels interrupts are zero;• the channels are in input capture mode;• the channels outputs are zero;• the channels pins are not controlled by TPM (ELS(n)B:ELS(n)A = 0:0).30.4.11 TPM InterruptsThis section describes TPM interrupts.Chapter 30 Timer/PWM Module (TPM)KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 515
