PORTx_PCRn field descriptions (continued)Field Description5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4PFEPassive Filter EnableThis bit is read only for pins that do not support a configurable passive input filter.Passive filter configuration is valid in all digital pin muxing modes.0 Passive input filter is disabled on the corresponding pin.1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Referto the device data sheet for filter characteristics.3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.2SRESlew Rate EnableThis bit is read only for pins that do not support a configurable slew rate.Slew rate configuration is valid in all digital pin muxing modes.0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.1PEPull EnableThis bit is read only for pins that do not support a configurable pull resistor. Refer to the Chapter of SignalMultiplexing and Signal Descriptions for the pins that support a configurable pull resistor.Pull configuration is valid in all digital pin muxing modes.0 Internal pullup or pulldown resistor is not enabled on the corresponding pin.1 Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as adigital input.0PSPull SelectThis bit is read only for pins that do not support a configurable pull resistor direction.Pull configuration is valid in all digital pin muxing modes.0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enablefield is set.1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable fieldis set.11.5.2 Global Pin Control Low Register (PORTx_GPCLR)Only 32-bit writes are supported to this register.Address: Base address + 80h offsetBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0W GPWE GPWDReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Memory map and register definitionKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012160 Freescale Semiconductor, Inc.
