I2Cx_FLT field descriptions (continued)Field DescriptionHardware sets this bit when the I2C bus's stop status is detected. The STOPF bit must be cleared bywriting 1 to it.0 No stop happens on I2C bus1 Stop detected on I2C bus5STOPIEI2C Bus Stop Interrupt EnableThis bit enables the interrupt for I2C bus stop detection.NOTE: To clear the I2C bus stop detection interrupt: In the interrupt service routine, first clear the STOPFbit by writing 1 to it, and then clear the IICIF bit in the status register. If this sequence is reversed,the IICIF bit is asserted again.0 Stop detection interrupt is disabled1 Stop detection interrupt is enabled4–0FLTI2C Programmable Filter FactorControls the width of the glitch, in terms of bus clock cycles, that the filter must absorb. For any glitchwhose size is less than or equal to this width setting, the filter does not allow the glitch to pass.00h No filter/bypass01-1Fh Filter glitches up to width of n bus clock cycles, where n=1-31d35.3.8 I2C Range Address register (I2Cx_RA)Address: 4006_6000h base + 7h offset = 4006_6007hBit 7 6 5 4 3 2 1 0Read RAD 0WriteReset 0 0 0 0 0 0 0 0I2Cx_RA field descriptionsField Description7–1RADRange Slave AddressThis field contains the slave address to be used by the I2C module. The field is used in the 7-bit addressscheme. Any nonzero write enables this register. This register's use is similar to that of the A1 register, butin addition this register can be considered a maximum boundary in range matching mode.0ReservedThis field is reserved.This read-only field is reserved and always has the value 0.Memory map and register descriptionsKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012598 Freescale Semiconductor, Inc.
