DMA_DARn field descriptions (continued)Field DescriptionAfter being written with one of the allowed values, bits 31-20 read back as the written value.After being written with any other value, bits 31-20 read back as an indeterminate value.23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)DSR and BCR are two logical registers that occupy one 32-bit address. DSRn occupiesbits 31–24, and BCRn occupies bits 23–0. DSRn contains flags indicating the channelstatus, and BCRn contains the number of bytes yet to be transferred for a given block.On the successful completion of the write transfer, BCRn decrements by 1, 2, or 4 for 8-bit, 16-bit, or 32-bit accesses, respectively. BCRn is cleared if a 1 is written toDSR[DONE].In response to an event, the DMA controller writes to the appropriate DSRn bit. Only awrite to DSRn[DONE] results in action. DSRn[DONE] is set when the block transfer iscomplete.When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 4 or 2 whenthe DMA is configured for 32-bit or 16-bit transfers, respectively, DSRn[CE] is set andno transfer occurs.Address: 4000_8000h base + 108h offset + (16d × i), where i=0d to 3dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0 CE BES BED 0REQBSYDONEBCRW w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RBCRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 23 DMA Controller ModuleKL04 Sub-Family Reference Manual, Rev. 3.1, November 2012Freescale Semiconductor, Inc. 325
