Deserial Serial Peripheral Interface (DSPI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 20-13When the DSPI is configured as a SPI master, the CTAS field in the command portion of the TX FIFOentry selects which of the DSPIx_CTAR registers is used on a per-frame basis. When the DSPI isconfigured as a SPI bus slave, the DSPIx_CTAR0 register is used.When the DSPI is configured as a DSI master, the DSICTAS field in the DSPI DSI configuration register(DSPIx_DSICR) selects which of the DSPIx_CTAR register is used. See Section 20.3.2.10, “DSPI DSIConfiguration Register (DSPIx_DSICR).” When the DSPI is configured as a DSI bus slave, theDSPIx_CTAR1 register is used.In CSI configuration, the transfer attributes are selected based on whether the current frame is SPI data orDSI data. SPI transfers in CSI configuration follow the protocol described for SPI configuration, and DSItransfers in CSI configuration follow the protocol described for DSI configuration. CSI configuration isonly valid in conjunction with master mode. See Section 20.4.5, “Combined Serial Interface (CSI)Configuration” for more details..Address:Base + 0x000C (DSPIx_CTAR0)Base + 0x0010 (DSPIx_CTAR1)Base + 0x0014 (DSPIx_CTAR2)Base + 0x0018 (DSPIx_CTAR3)Base + 0x001C (DSPIx_CTAR4)Base + 0x0020 (DSPIx_CTAR5)Base + 0x0024 (DSPIx_CTAR6)Base + 0x0028 (DSPIx_CTAR7)Access: R/W0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R DBR FMSZ CPOL CPHA LSBFE PCSSCK PASC PDT PBRWReset 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R CSSCK ASC DT BRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 20-5. DSPI Clock and Transfer Attributes Registers 0–7 (DSPIx_CTARn)
