Deserial Serial Peripheral Interface (DSPI)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 20-2914TRRETrigger reception enable. Enables the DSPI to initiate a transfer when an external trigger signal is received. Thebit is only valid in DSI configuration. See Section 20.4.4.5, “DSI Transfer Initiation Control,” for more information.0 Trigger signal reception disabled1 Trigger signal reception enabled15CIDChange in data transfer enable. Enables a change in serialization data to initiate a transfer. The bit is used inmaster mode in DSI and CSI configurations to control when to initiate transfers. When the CID bit is set,serialization is initiated when the current DSI data differs from the previous DSI data shifted out. TheDSPIx_COMPR is compared with the DSPIx_SDR or DSPIx_ASDR to detect a change in data. SeeSection 20.4.4.5, “DSI Transfer Initiation Control,” for more information.0 Change in data transfer operation disabled1 Change in data transfer operation enabled16DCONTDSI continuous peripheral chip select enable. Enables the PCSx signals to remain asserted between transfers.The DCONT bit only affects the PCS signals in DSI master mode. See Section 20.4.7.5, “Continuous SelectionFormat,” for details.0 Return peripheral chip select signals to their inactive state after transfer is complete1 Keep peripheral chip select signals asserted after transfer is complete17–19DSICTAS[0:2]DSI clock and transfer attributes select. The DSICTAS field selects which of the DSPIx_CTARs is used toprovide transfer attributes in DSI configuration. The DSICTAS field is used in DSI master mode. In DSI slavemode, the DSPIx_CTAR1 is always selected. The following table lists the DSICTAS to DSPIx_CTARs mapping.20–23 Reserved24–25 Reserved, but implemented. These bits are writable, but have no effect.26–31DPCSxDSI peripheral chip select n. The DPCS bits select which of the PCSx signals to assert during a DSI transfer.The DPCS bits assert and negate the PCSx signals in DSI master mode only.0 Negate PCSx1 Assert PCSxTable 20-12. DSPIx_DSICR Field Descriptions (continued)Field DescriptionDSICTAS DSI Clock and Transfer AttributesControlled by000 DSPIx_CTAR0001 DSPIx_CTAR1010 DSPIx_CTAR2011 DSPIx_CTAR3100 DSPIx_CTAR4101 DSPIx_CTAR5110 DSPIx_CTAR6111 DSPIx_CTAR7
