Enhanced Direct Memory Access (eDMA)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 9-13EDMA_SERQR are provided so that the request enable for a single channel can easily be modified withoutthe need to perform a read-modify-write sequence to the EDMA_ERQRH and EDMA_ERQRL.Both the DMA request input signal and this enable request flag must be asserted before a channel’shardware service request is accepted. The state of the eDMA enable request flag does not affect a channelservice request made explicitly through software or a linked channel request.As a given channel completes the processing of its major iteration count, there is a flag in the transfercontrol descriptor that can affect the ending state of the EDMA_ERQR bit for that channel. If theTCD.D_REQ bit is set, then the corresponding EDMA_ERQR bit is cleared after the major loop isAddress: Base + 0x0008 Access: User R/W0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R ERQ63ERQ62ERQ61ERQ60ERQ59ERQ58ERQ57ERQ56ERQ55ERQ54ERQ53ERQ52ERQ51ERQ50ERQ49ERQ48WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R ERQ47ERQ46ERQ45ERQ44ERQ43ERQ42ERQ41ERQ40ERQ39ERQ38ERQ37ERQ36ERQ35ERQ34ERQ33ERQ32WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 9-4. eDMA Enable Request High Register (EDMA_ERQRH)Address: Base + 0x000C Access: User R/W0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R ERQ31ERQ30ERQ29ERQ28ERQ27ERQ26ERQ25ERQ24ERQ23ERQ22ERQ21ERQ20ERQ19ERQ18ERQ17ERQ16WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R ERQ15ERQ14ERQ13ERQ12ERQ11ERQ10ERQ09ERQ08ERQ07ERQ06ERQ05ERQ04ERQ03ERQ02ERQ01ERQ00WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Figure 9-5. eDMA Enable Request Low Register (EDMA_ERQRL)Table 9-4. EDMA_ERQRH, EDMA_ERQRL Field DescriptionsField Description0–63ERQnEnable DMA hardware service request n.0 The DMA request signal for channel n is disabled.1 The DMA request signal for channel n is enabled.
