Enhanced Direct Memory Access (eDMA)MPC5566 Microcontroller Reference Manual, Rev. 29-40 Freescale Semiconductor4. Write the 32-byte TCD for each channel that can request service.5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers.6. Request channel service by either software (setting the TCD.START bit) or by hardware (slavedevice asserting its eDMA peripheral request signal).After any channel requests service, a channel is selected for execution based on the arbitration and prioritylevels written into the programmer's model. The eDMA engine reads the entire TCD, including theprimary transfer control parameter shown in Table 9-22, for the selected channel into its internal addresspath module. As the TCD is being read, the first transfer is initiated on the system bus unless aconfiguration error is detected. Transfers from the source (as defined by the source address, TCD.SADDR)to the destination (as defined by the destination address, TCD.DADDR) continue until the specifiednumber of bytes (TCD.NBYTES) have been transferred. When the transfer is complete, the eDMAengine's local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memoryand any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further postprocessing is executed: for example, interrupts, major loop channel linking, and scatter/gather operations,if enabled.Figure 9-27 shows how each DMA request initiates one minor loop transfer (iteration) without CPUintervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMApreemption is allowed. The number of minor loops in a major loop is specified by the beginning iterationcount (biter).Table 9-22. TCD Primary Control and Status FieldsTCD FieldName DescriptionSTART Control bit to explicitly start channel when using a softwareinitiated DMA service (Automatically cleared by hardware)ACTIVE Status bit indicating the channel is currently in executionDONE Status bit indicating major loop completion (Cleared by softwarewhen using a software initiated DMA service)D_REQ Control bit to disable DMA request at end of major loopcompletion when using a hardware-initiated DMA serviceBWC Control bits for “throttling” bandwidth control of a channelE_SG Control bit to enable scatter-gather featureINT_HALF Control bit to enable interrupt when major loop is half completeINT_MAJ Control bit to enable interrupt when major loop completes
