Enhanced Modular Input/Output Subsystem (eMIOS)MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 17-5117.4.4.4.13 Center-Aligned Output Pulse-Width Modulation with Dead-time Mode(OPWMC)The following table lists the center-aligned output pulse-width modulation with dead-time mode settings:This operating mode generates a center-aligned PWM with dead-time insertion in the leading- ortrailing-edge.The selected counter bus must be running an up/down time base, as shown in Figure 17-33. BSL[0:1] bitsselect the time base. Register A1 contains the ideal duty cycle for the PWM signal and is compared withthe selected time base. Register B1 contains the dead time value and is compared with the internal counter.For a leading edge dead time insertion, the output PWM duty cycle is equal to the difference betweenregister A1 and register B1, and for a trailing edge dead time insertion, the output PWM duty cycle is equalto the sum of register A1 and register B1. MODE[6] bit selects between trailing and leading dead timeinsertion, respectively.NOTESynchronize the internal prescaler of the OPWMCB channel with the MCBchannel prescaler and set them to the same value. This allows the A1 and B1registers to represent the same time scale for duty cycle and dead timeinsertion.When operating with leading edge dead time insertion, the first match between A1 and the selected timebase clears the internal counter and switches the selected time base to the internal counter. When a matchoccurs between register B1 and the selected time base, the output flip-flop is set to the value of the EDPOLbit and the time base is switched to the selected counter bus. In the next match between register A1 andthe selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequencerepeats continuously.When operating with trailing edge dead time insertion, the first match between A1 and the selected timebase sets the output flip-flop to the value of the EDPOL bit. In the next match between register A1 and theselected time base, the internal counter is cleared and the selected time base is switched to the internalcounter. When a match occurs between register B1 and the selected time base, the output flip-flop is set tothe complement of the EDPOL bit and the time base is switched to the selected counter bus. This sequencerepeats continuously.FLAG can be generated in the trailing edge of the output PWM signal when MODE[5] is cleared, or inboth edges, when MODE[5] is set.Table 17-26. OPWMC Operating ModeMODE[0:6] Unified Channel OPWMC Operating Mode0b0011100 Center-aligned output pulse-width modulation. FLAG set in trailing edge, trailing edge dead-time.0b0011101 Center-aligned output pulse-width modulation. FLAG set in trailing edge, leading-edge dead-time.0b0011110 Center-aligned output pulse-width modulation. FLAG set in both edges, trailing edge dead-time.0b0011111 Center-aligned output pulse-width modulation. FLAG set in both edges, leading edge dead-time.
