Enhanced Modular Input/Output Subsystem (eMIOS)MPC5566 Microcontroller Reference Manual, Rev. 217-16 Freescale Semiconductor9–12IF[0:3]Input filter. Controls the programmable input filter, selecting the minimum input pulse-width that can passthrough the filter, as shown below. For output modes, these bits have no meaning.13FCKFilter clock select. Selects the clock source for the programmable input filter.0 Prescaled clock1 Main clock14FENFLAG enable. Allows the unified channel FLAG bit to generate an interrupt signal or a DMA request signal(The type of signal to be generated is defined by the DMA bit).0 Disable (FLAG does not generate an interrupt or DMA request)1 Enable (FLAG generates an interrupt or DMA request)15–17 Reserved.18FORCMAForce match A. For output modes, the FORCMA bit is equivalent to a successful comparison on comparatorA (except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is validfor every output operating mode which uses comparator A, otherwise it has no effect.0 Has no effect1 Force a match at comparator AFor input modes, the FORCMA bit is not used and writing to it has no effect.19FORCMBForce match B. For output modes, the FORCMB bit is equivalent to a successful comparison on comparatorB (except that the FLAG bit is not set). This bit is cleared by reset and is always read as zero. This bit is validfor every output operating mode which uses comparator B, otherwise it has no effect.0 Has no effect1 Force a match at comparator BFor input modes, the FORCMB bit is not used and writing to it has no effect.20 Reserved.Table 17-9. EMIOS_CCRn Field Description (continued)Field DescriptionIF[0:3]11 Filter latency is three clock cycles.Minimum Input Pulse Width[filter clock periods]0000 Bypassed22 The input signal is synchronized before arriving at thedigital filter.0001 2 filter clock periods0010 4 filter clock periods0100 8 filter clock periods1000 16 filter clock periodsall others Invalid values
