MPC5566 Register MapMPC5566 Microcontroller Reference Manual, Rev. 2A-38 Freescale SemiconductorReserved — — Base + (0x001C–0x001E)Software watchdog timer interrupt register ECSM_SWTIR 1 8-bit Base + 0x001FReserved — Base + (0x0020–0x0023)FEC Burst Optimization Master Control register FBOMCR 32-bit Base + 0x0024Reserved — — Base + (0x0028–0x0042)ECC configuration register ECSM_ECR 8-bit Base + 0x0043Reserved — — Base + (0x0044–0x0046)ECC status register ECSM_ESR 8-bit Base + 0x0047Reserved — — Base + (0x0048–0x0049)ECC error generation register ECSM_EEGR 16-bit Base + 0x004AReserved — — Base + (0x004C–0x004F)Flash ECC address register ECSM_FEAR 32-bit Base + 0x0050Reserved — — Base + (0x0054–0x0055)Flash ECC master number register ECSM_FEMR 8-bit Base + 0x0056Flash ECC attributes register ECSM_FEAT 8-bit Base + 0x0057Flash ECC data register high ECSM_FEDRH 32-bit Base + 0x0058Flash ECC data register low ECSM_FEDRL 32-bit Base + 0x005CRAM ECC address register ECSM_REAR 32-bit Base + 0x0060Reserved — — Base + (0x0064–0x0065)RAM ECC master number register ECSM_REMR 8-bit Base + 0x0066RAM ECC attributes register ECSM_REAT 8-bit Base + 0x0067RAM ECC data register high ECSM_REDRH 32-bit Base + 0x0068RAM ECC data register low ECSM_REDRL 32-bit Base + 0x006CReserved — — (Base + 0x0070)–0xFFF4_3FFFEnhanced Direct Memory Access (eDMA)Chapter 9, “Enhanced Direct Memory Access (eDMA)” 0xFFF4_4000Control register EDMA_CR 32-bit Base + 0x0000Error status register EDMA_ESR 32-bit Base + 0x0004Reserved — — Base + (0x0008)Enable request register low EDMA_ERQRL 32-bit Base + 0x000CReserved — — Base + (0x0010)Enable error interrupt register low EDMA_EEIRL 32-bit Base + 0x0014Table A-2. MPC5566 Detailed Register Map (continued)Register Description Register Name UsedSize Address
