MPC5566 Microcontroller Reference Manual, Rev. 2Freescale Semiconductor 22-13Address: Base + 0x0004 Access: User read/write0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R PRESDIV RJW PSEG1 PSEG2WReset1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R BOFFMSKERRMSKCLK_SRC LPB TWRNMSKRWRNMSK0 0 SMP BOFFREC TSYN LBUF LOM PROPSEGWReset1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 CANx_CR is unaffected by soft reset (which occurs when CAN_MCR[SOFTRST] is asserted).Figure 22-4. Control Register (CANx_CR)Table 22-8. CANx_CR Field DescriptionsBits Description0–7PRESDIV[0:7]Prescaler division factor. Defines the ratio between the CPI clock frequency and the serial clock (SCK)frequency. The SCK period defines the time quantum of the CAN protocol. For the reset value, the SCKfrequency is equal to the CPI clock frequency. The maximum value of this register is 0xFF, that gives aminimum SCK frequency equal to the CPI clock frequency divided by 256. For more information, seeSection 22.4.5.4, “Protocol Timing.”8–9RJW[0:1]Resync jump width. Defines the maximum number of time quanta 1 that a bit time can be changed by onere-synchronization. The valid programmable values are 0–3.10–12PSEG1[0:2]Phase segment 1. Defines the length of phase buffer segment 1 in the bit time. The valid programmablevalues are 0–7.13–15PSEG2[0:2]Phase segment 2. Defines the length of phase buffer segment 2 in the bit time. The valid programmablevalues are 1–7.16BOFFMSKBus off mask. Provides a mask for the bus off interrupt.0 Bus off interrupt disabled1 Bus off interrupt enabled17ERRMSKError mask. Provides a mask for the error interrupt.0 Error interrupt disabled1 Error interrupt enabled18CLK_SRCCAN engine clock source. Selects the clock source to the CAN Protocol Interface (CPI) to be either thesystem clock (driven by the PLL) or the crystal oscillator clock. The selected clock is fed into the prescalerto generate the serial clock (SCK).0 = The CAN engine clock source is the oscillator clock1 = The CAN engine clock source is the system clockS-clock frequency CPI clock frequencyPRESDIV 1+-----------------------------------------------------=Resync Jump Width RJW + 1=Phase Buffer Segment 1 PSEG1 + 1( ) Time Quanta×=Phase Buffer Segment 2 PSEG2 + 1( ) Time Quanta×=
