NXP Semiconductors QorIQ LS1012A Reference Manual

21.7.5.3 Exiting DMA mode, system requirement considerationsAs described above, the final transfers of both TX and RX transfers need to be handledvia interrupt by the CPU. To change from DMA to interrupt driven transfers in the I2Cmodule, you have to disable the DMAEN bit in the IBCR register. The trigger to exit theDMA mode is that the programmed DMA Transfer Control Descriptor (TCD) hascompleted all its transfers to/from the I2C module.After the last DMA write (TX mode) to the I2C the module will immediately start thenext I2C-bus transfer. The same is true for receive mode. After the DMA read from theIBDR register the module initiates the next I2C-bus transfer. This results in two possiblescenarios in the DMA mode exiting scheme.1. Fast reactionThe DMAEN bit is cleared before the next I2C-bus transfer completes. In this casethe module will raise an interrupt request to the CPU which can be servicednormally.2. Slow reactionThe DMAEN bit is cleared after the next I2C-bus transfer has already completed. Inthis case, the module will not raise an interrupt request to the CPU. Instead the TCFbit can be read to determine that the transfer completed and the module is ready forfurther transfer.What is fast/slow reaction?The reaction time TR for the system to disable DMAEN after the last DMA controlleraccess to the I2C is the time required for one byte transfer over the I2C. For 'fast reaction'the disabling has to occur before the 9th bit of the data transfer which is the ACK bit. Sothe time available is eight times the SCL period.In fast mode, with 400kbit/s, TSCL is 2.5μs, so TR is 20μs.Depending on the system and DMA controller there are different possibilities for the de-assertion of DMAEN. Three options are:1. CPU intervention via InterruptThe DMA controller is programmed to signal an interrupt to the CPU which is thenresponsible for the de-assertion of DMAEN. This scheme should be supported bymost systems but it can result in a slow reaction time if other higher priorityChapter 21 Inter-Integrated Circuit (I2C)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1037