NXP Semiconductors QorIQ LS1012A Reference Manual

32.3.30.2 FunctionThe Endpoint status register is not defined in the EHCI specification. This register is onlyused in device mode.32.3.30.3 DiagramBits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R Reserved ETBRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R Reserved ERBRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 032.3.30.4 FieldsField Function0-9—-Reserved, should be cleared10-15ETBRETBREndpoint transmit buffer ready. One bit for each Endpoint indicates status of the respective Endpointbuffer. This bit is set by the hardware as a response to receiving a command from a corresponding bit inthe ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIMEregister and Endpoint indicating ready. This delay time varies based upon the current USB traffic and thenumber of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMAsystem, or through the ENDPTFLUSH register. ETBR[5] (bit 21 of the register) corresponds to Endpoint5.Note that these bits are momentarily cleared by hardware during hardware Endpoint re-primingoperations when a dTD is retired, and the dQH is updated.16-25—-Reserved, should be cleared26-31ERBRERBREndpoint receive buffer ready. One bit for each Endpoint indicates status of the respective Endpointbuffer. This bit is set by the hardware as a response to receiving a command from a corresponding bit inthe ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIMEregister and Endpoint indicating ready. This delay time varies based upon the current USB traffic and thenumber of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMAsystem, or through the ENDPTFLUSH register. ERBR[5] corresponds to Endpoint 5.USB register descriptionsQorIQ LS1012A Reference Manual, Rev. 1, 01/20181952 NXP Semiconductors