5. A non-posted request can bypass a completion if the relaxed ordering bit is set (that is, RO = 1).6. A read completion, I/O write completion, or configuration write completion cannot bypass a posted request if the relaxedordering bit is cleared (that is, RO = 0).7. A read completion, I/O write completion, or configuration write completion can bypass a posted request if the relaxedordering bit is set (that is, RO = 1).8. Regardless of the setting of the relaxed ordering bit, a read completion cannot bypass another read completion.In general, the following points summarize the ordering rules for sending the nextoutstanding request:• A posted request can bypass all other transactions except another posted request.• A non-posted request cannot bypass posted or other non-posted requests, but it canbypass a completion if the relaxed ordering (RO) bit is set.(See Table 25-5).• A completion can bypass posted requests if the relaxed ordering (RO) bit is set andcan bypass non-posted transactions. However, a completion cannot bypass othercompletions.25.6.1.3 Internal Address Translation UnitThe core uses the iATU to replace the TLP address and TLP header fields in the currentTLP request header. This section presents the following topics:• iATU Overview• Programming the iATU• Outbound iATU Operation• Inbound iATU Operation25.6.1.3.1 iATU OverviewAddress translation is used for mapping different address ranges to different memoryspaces supported by your application. A typical example maps the internal platformmemory space to PCI memory space. The iATU supports type translation. Withoutaddress translation, your application address is passed to/from the PCIe TLPs directlythrough the internal platform . You can program the iATU to implement your ownaddress translation scheme without the need for additional external hardware.Inbound Features:• Match mode operation for MEM TLPs. No translation for completions. SelectableBAR Match mode operation for MEM TLPs.NOTEAddress match mode can only be used in RC mode; BARmatch mode must be used in EP mode.Chapter 25 PCI Express Interface ControllerQorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1401