NXP Semiconductors QorIQ LS1012A Reference Manual

23.3.4.2 Self refresh and Frequency change entry/exitAs described in Power saving general, the MMDC supports two mechanisms that willcause the DDR device to enter self-refresh mode:• LPMD (Low Power Mode) - For power saving purposes• DVFS (Dynamic Voltage and Frequency Change) - For clock frequency changesWhile the DDR device is in self-refresh mode, there is no need to provide periodicrefresh commands.The MMDC treats hardware/software handshaking of LPMD/DVFS in the same manner:• Upon the assertion of LPMD/DVFS request, the following is done:• The MMDC blocks any further AXI accesses even before the acknowledge isasserted• Completes all opened AXI accesses• Closes (precharge) all banks in the appropriate timing• Drives self-refresh command by deasserting clock enable signal(DRAM_SDCKE is driven to "0") together with a refresh command. This occursafter satisfying tRP/tRPA from the precharge all command.• Deasserts the clock that is driven to the DDR device• Asserts LPMD/DVFS acknowledge (LPACK/DVACK)• Allows deassertion of the operating clock of the MMDC (AXI clock)• Upon the deassertion of LPMD/DVFS request, the following is done:• Operating clock of the MMDC must be turned on before LPMD/DVFS isdeasserted• Starts driving the clock (CK) to the DDR device• After satisfying tCKSRX from clock renewal the clock enable signal(DRAM_SDCKE) is asserted• LPMD/DVFS acknowledge (LPACK/DVACK) is deasserted• After satisfying tXS from the assertion of DRAM_SDCKE, a refresh commandis driven to the DDR device.• If ZQ calibration is enabled then tRFC is satisfied from the refresh command anda long ZQ command is driven.• tZQoper idle cycles are counted after the ZQ command.• After satisfying tDLLK from the assertion DRAM_SDCKE, the MMDC returnsto normal operation.The figure below shows the timing diagram of the hardware/software handshaking ofLPMD/DVFS:Chapter 23 Multi Mode DDR Controller (MMDC)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1087