NXP Semiconductors QorIQ LS1012A Reference Manual

Each OCRAM occupies a 64 KB of address region and the start address of each OCRAM(64 KB each) in the memory map is given below:• OCRAM1: 0x1000_0000• OCRAM2: 0x1001_0000.NOTEThe OCRAM1 and OCRAM2 memory content is not initializedto zero by the chip. The software must initialize both OCRAM1and OCRAM2 in full width (64-bit) access and then perform awrite to bit 5 and 6 at address 0x2014_0534 and 0x2014_0544,respectively with the value 0x0 to clear the single and multi-bitECC errors for OCRAM1 and OCRAM2. Also, the ECC errorinterrupt needs to be cleared in GIC (MBEE). Once completed,the host processor enables interrupt related to ECC errors fromOCRAM1 and OCRAM27.3 Miscellaneous System Control Module (MSCM)The MSCM (platform control) stores the status and address attributes of a transaction to aperipheral which was blocked by the CSU. The MSCM also enables CSU interrupts.7.3.1 MSCM Access Control and TrustZone Security(ACTZS)Memory Map/Register DefinitionThe ACTZS configuration portion of the MSCM programming model map is shown inthe table below. It is partitioned into two sections:Offset addresses 0xC00 - 0xC18 define interrupt configurability of CSU related accessviolation reporting.Offset addresses 0xD00 - 0xDDC contain captured access address and attributeinformation for CSL-detected violations.Attempted writes to read-only registers are simply ignored (RO/WI). This sectioncontains the target access fault information like CSLn attribute check logic plus an arrayof 128-bit register structures containing captured CSLn fault information.All the register accesses are privilege/supervisorMiscellaneous System Control Module (MSCM)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018276 NXP Semiconductors