NXP Semiconductors QorIQ LS1012A Reference Manual

Section number Title Page32.8.5 Managing transfers with transfer descriptors.................................................................................................208932.8.5.1 Software link pointers................................................................................................................ 208932.8.5.2 Building a transfer descriptor.....................................................................................................209032.8.5.3 Executing a transfer descriptor.................................................................................................. 209032.8.5.4 Transfer completion................................................................................................................... 209132.8.5.5 Flushing/depriming an endpoint................................................................................................ 209232.8.5.6 Device error matrix.................................................................................................................... 209232.8.6 Servicing interrupts........................................................................................................................................ 209332.8.6.1 High-frequency interrupts.......................................................................................................... 209332.8.6.2 Low-frequency interrupts...........................................................................................................209332.8.6.3 Error interrupts........................................................................................................................... 209432.9 Deviations from the EHCI specifications..................................................................................................................... 209432.9.1 Embedded transaction translator function......................................................................................................209532.9.1.1 Capability registers.................................................................................................................... 209532.9.1.2 Operational registers.................................................................................................................. 209532.9.1.3 Discovery differences ............................................................................................................... 209532.9.1.4 Data structures............................................................................................................................209632.9.1.5 Operational model......................................................................................................................209732.9.1.5.1 Microframe pipeline............................................................................................209732.9.1.5.2 Split state machines.............................................................................................209832.9.1.5.3 Asynchronous transaction scheduling and buffer management..........................209832.9.1.5.4 Periodic transaction scheduling and buffer management................................... 209932.9.1.5.5 Multiple transaction translators...........................................................................209932.9.2 Device operation............................................................................................................................................ 209932.9.3 Non-zero fields the register file..................................................................................................................... 209932.9.4 SOF interrupt..................................................................................................................................................210032.9.5 Embedded design........................................................................................................................................... 210032.9.5.1 Frame adjust register.................................................................................................................. 210032.9.6 Miscellaneous variations from EHCI.............................................................................................................2100QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 153