NXP Semiconductors QorIQ LS1012A Reference Manual

All reserved register fields must be preserved on register writes (read-modified-write).28.5.1 SerDes Memory mapSerDes base address: 1EA_0000hOffset Register Width(In bits)Access Reset value0h SerDes PLL1 Reset Control Register (PLL1RSTCTL) 32 RW 0000_0020h4h SerDes PLL1 Control Register 0 (PLL1CR0) 32 RW 8080_0008h8h SerDes PLL1 Control Register 1 (PLL1CR1) 32 RW 0800_0000h18h SerDes PLL1 Control Register 5 (PLL1CR5) 32 RW 0000_0000h20h SerDes PLL2 Reset Control Register (PLL2RSTCTL) 32 RW 0000_0020h24h SerDes PLL2 Control Register 0 (PLL2CR0) 32 RW 8080_0008h28h SerDes PLL2 Control Register 1 (PLL2CR1) 32 RW 0800_0000h38h SerDes PLL2 Control Register 5 (PLL2CR5) 32 RW 0000_0000h90h SerDes Transmit Calibration Control Register (TCALCR) 32 RW 0000_0000h94h SerDes Transmit Calibration Control Register 1 (TCALCR1) 32 RW 0000_0000hA0h Receive Calibration Control Register (RCALCR) 32 RW 0000_0000hA4h SerDes Receive Calibration Control Register 1 (RCALCR1) 32 RW 0000_0000hB0h General Control Register 0 (GR0) 32 RW 0000_0000h200h Protocol Configuration Register 0 (PCCR0) 32 RW 0000_0000h208h Protocol Configuration Register 2 (PCCR2) 32 RW 0000_0000h220h Protocol Configuration Register 8 (PCCR8) 32 RW 0000_0000h800h General Control Register 0 - Lane A (LNAGCR0) 32 RW 1104_0000h804h General Control Register 1 - Lane A (LNAGCR1) 32 RW 004C_4011h80Ch Speed Switch Control Register 0 - Lane A (LNASSCR0) 32 RW 9800_2B00h810h Receive Equalization Control Register 0 - Lane A (LNARECR0) 32 RW 0000_001Fh814h Receive Equalization Control Register 1- Lane A (LNARECR1) 32 RO 0000_0008h818h Transmit Equalization Control Register 0 - Lane A (LNATECR0) 32 RW 1028_3000h81Ch Speed Switch Control Register 1- Lane 0 (LNASSCR1) 32 RW 0000_0000h820h TTL Control Register 0 - Lane A (LNATTLCR0) 32 RW 0000_0400h83Ch Test Control/Status Register 3 - Lane A (LNATCSR3) 32 RW 0400_0000h840h General Control Register 0 - Lane B (LNBGCR0) 32 RW 1104_0000h844h General Control Register 1 - Lane B (LNBGCR1) 32 RW 004C_4011h84Ch Speed Switch Control Register 0 - Lane B (LNBSSCR0) 32 RW 9800_2B00h850h Receive Equalization Control Register 0 - Lane B (LNBRECR0) 32 RW 0000_001Fh854h Receive Equalization Control Register 1- Lane B (LNBRECR1) 32 RO 0000_0008h858h Transmit Equalization Control Register 0 - Lane B (LNBTECR0) 32 RW 1028_3000h85Ch Speed Switch Control Register 1- Lane 0 (LNBSSCR1) 32 RW 0000_0000h860h TTL Control Register 0 - Lane B (LNBTTLCR0) 32 RW 0000_0400hTable continues on the next page...Chapter 28 SerDes ModuleQorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1597