NXP Semiconductors QorIQ LS1012A Reference Manual

27.3.13 AXI cache control register (AXICC)27.3.13.1 OffsetRegister OffsetAXICC BCh27.3.13.2 FunctionThis register controls the value of the AWCACHE and ARCACHE used to distinguisheach address operation on the address bus.AWCACHE/ARCACHE control (Non AHCI standard)Both AWCACHE and ARCACHE can be controlled during header, command, and statusof the data phase AXI bus operations. The values driven onto these signals are controlledby the AXI cache control register for operations related to the header, physical regiondescription, command, and status operations. The values driven onto these signals duringa data operation can be further controlled from the relevant PRDT entry as shown inTable 27-13. Note that this control is not an AHCI standard.The following table summarizes each of the possible attributes that can be set through thecache bits.Table 27-6. Attributes listARCACHE[3:0]/AWCACHE[3:0] TransactionattributesWA RA C B0 0 0 0 Non-cacheable andnon-bufferable0 0 0 1 Bufferable only0 0 1 0 Cacheable, but do notallocate0 0 1 1 Cacheable andbufferable, but do notallocate0 1 0 0 Reserved0 1 0 1 Reserved0 1 1 0 Cacheable write-through, allocate onreads onlyTable continues on the next page...SATA AHCI register descriptionsQorIQ LS1012A Reference Manual, Rev. 1, 01/20181536 NXP Semiconductors