NXP Semiconductors QorIQ LS1012A Reference Manual

Field Function—24-27—Reserved28XSPIExtended SPI ModeThis bit enables usage of CTARE (Command and Transfer Attribute Register Extended) Registers.CTARE registers allow the user to send up to 32 bit SPI frames. Command Cycling is also enabled whichallows the user to send multiple Data Frames using a single Command Frame. When MCR[DIS_TXF] isasserted, the Extended SPI Mode cannot be used to transmit SPI frames which are more than 16 bits insize.0b - Normal SPI Mode. Frame size can be up to 16 bits. Command Cycling is not available in thismode.1b - Extended SPI Mode. Up to 32 bit SPI Frames along with Command Cycling is Enabled.29—Reserved30PESParity Error StopControls SPI operation when a parity error is detected in a received SPI frame.0b - SPI frame transmission continues.1b - SPI frame transmission stops.31HALTHaltThe HALT bit starts and stops frame transfers. See Start and Stop of Module transfers0b - Start transfers.1b - Stop transfers.30.4.3 Transfer Count Register (TCR)30.4.3.1 OffsetRegister OffsetTCR 8h30.4.3.2 FunctionTCR contains a counter that indicates the number of SPI transfers made. The transfercounter is intended to assist in queue management. Do not write the TCR when themodule is in the Running state.SPI register descriptionsQorIQ LS1012A Reference Manual, Rev. 1, 01/20181816 NXP Semiconductors