NXP Semiconductors QorIQ LS1012A Reference Manual

Offset Register Width(In bits)Access Reset value103h Channel Priority Register (DCHPRI0) 8 RW 00h104h Channel Priority Register (DCHPRI7) 8 RW 07h105h Channel Priority Register (DCHPRI6) 8 RW 06h106h Channel Priority Register (DCHPRI5) 8 RW 05h107h Channel Priority Register (DCHPRI4) 8 RW 04h108h Channel Priority Register (DCHPRI11) 8 RW 0Bh109h Channel Priority Register (DCHPRI10) 8 RW 0Ah10Ah Channel Priority Register (DCHPRI9) 8 RW 09h10Bh Channel Priority Register (DCHPRI8) 8 RW 08h10Ch Channel Priority Register (DCHPRI15) 8 RW 0Fh10Dh Channel Priority Register (DCHPRI14) 8 RW 0Eh10Eh Channel Priority Register (DCHPRI13) 8 RW 0Dh10Fh Channel Priority Register (DCHPRI12) 8 RW 0Ch110h Channel Priority Register (DCHPRI19) 8 RW 13h111h Channel Priority Register (DCHPRI18) 8 RW 12h112h Channel Priority Register (DCHPRI17) 8 RW 11h113h Channel Priority Register (DCHPRI16) 8 RW 10h114h Channel Priority Register (DCHPRI23) 8 RW 17h115h Channel Priority Register (DCHPRI22) 8 RW 16h116h Channel Priority Register (DCHPRI21) 8 RW 15h117h Channel Priority Register (DCHPRI20) 8 RW 14h118h Channel Priority Register (DCHPRI27) 8 RW 1Bh119h Channel Priority Register (DCHPRI26) 8 RW 1Ah11Ah Channel Priority Register (DCHPRI25) 8 RW 19h11Bh Channel Priority Register (DCHPRI24) 8 RW 18h11Ch Channel Priority Register (DCHPRI31) 8 RW 1Fh11Dh Channel Priority Register (DCHPRI30) 8 RW 1Eh11Eh Channel Priority Register (DCHPRI29) 8 RW 1Dh11Fh Channel Priority Register (DCHPRI28) 8 RW 1Ch140h - 15Fh Channel n Master ID Register (DCHMID0 - DCHMID31) 8 RW 00h1000h TCD Source Address (TCD0_SADDR) 32 RW Seedescription.1004h TCD Transfer Attributes (TCD0_ATTR) 16 RW Seedescription.1006h TCD Signed Source Address Offset (TCD0_SOFF) 16 RW Seedescription.1008h TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBYTES_MLNO)32 RW Seedescription.1008h TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled andOffset Disabled) (TCD0_NBYTES_MLOFFNO)32 RW Seedescription.Table continues on the next page...Memory map/register definitionQorIQ LS1012A Reference Manual, Rev. 1, 01/2018624 NXP Semiconductors