NXP Semiconductors QorIQ LS1012A Reference Manual

Table 4-10. RCW Field Descriptions (continued)Bit(s) (of0-511)Field Name Description Notes/comments0 Secure boot is not enabled1 Secure boot is enabled203-215 Reserved. Must be set to all 0's.216-223 Reserved. Must be set to all 0's.CLOCKING CONFIGURATION (BITS 224-255)224-231 Reserved. Must be set to all 0's.232 Reserved. Must be set to 0.233 Reserved. Must be set to 0.234 Reserved. Must be set to 0.235 Reserved. Must be set to 0.236-241 Reserved. Must be set to all 0's.242-243 SYS_PLL_SPD System PLL Speed Select Must be set to 01.244 CGA_PLL1_SPD Cluster Group A PLL1 SpeedSelectThis bit must be set based on the cluster group A PLL1speed.0 High-speed operation (>= 1 GHz)1 Low-speed operation (< 1 GHz)NOTE: Refer Differences between silicon revisions1.0 and 2.0 for the implementation in siliconrevision 1.0.245-255 Reserved. Must be set to all 0's.MEMORY AND HIGH SPEED I/O CONFIGURATION (BITS 256-287)256-263 Reserved. Must be set to all 0's.264 HOST_AGT_PEX Host/Agent PEX. ConfiguresHost/Agent mode for the PCIExpress interface.Options:0 Host mode1 Agent mode265-287 Reserved. Must be set to all 0's.GENERAL PURPOSE INFORMATION (BITS 288-319)288-319 GP_INFO General purpose information. This bit has no effect on functional logic; it may be usedby software.ENGINEERING USE CONFIGURATION (BITS 320-351)320-351 Reserved. Must be set to all 0's.GROUP A PIN CONFIGURATION (BITS 352-383)352-353 Reserved. Must be set to 00.354 SDHC2_EXT_CLK This field configures thefunctionality ofSDHC2_EXT_CLK pinstogether withSDHC2_BASE_BASE field.Options:0 GPIO1[29]1 FTM2_CH3NOTE: This field is ignored if SDHC2_BASE_BASEis not equal to 2'b00355 SDHC2_EXT_CMD This field configures thefunctionality ofOptions:0 GPIO1[24]Table continues on the next page...Chapter 4 Reset, Clocking, and InitializationQorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 239