NXP Semiconductors QorIQ LS1012A Reference Manual

Table 25-2. PCI Express Interface Signals—Detailed Signal Descriptions(continued)Signal I/O DescriptionStateMeaningAsserted/Negated—Represents data being transmitted to the PCI Express interface.Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 3.0.SD_TX[n]_N O Transmit data, negative. The transmit data signals carry PCI Express packet information.StateMeaningAsserted/Negated—Represents the inverse of data being transmitted to the PCI Expressinterface.Timing Assertion/Negation—As described in the PCI Express Base Specification, Revision 3.0.25.4 Memory map/register overview25.4.1 PCI Express configuration registersThe PCI Express module supports the same configuration registers in both the internalmemory map and in PCI Express configuration space. They differ only in whether theyare accessed from an internal initiator or from an external initiator on the PCI Expressinterface. With the exception of the registers in the PEX module internal configurationspace, the configuration registers are specified by the PCI Express specification for everyPCI Express device. The registers in the PEX module internal configuration space areused for chip-specific functionality and are not defined by the PCI Express specification.Table 25-3. PCI Express memory mapRegister space Offset NEXT pointer NotesType 0 configuration header 0x000 0x40 EP use Type 0Type 1 configuration header 0x000 0x40 RC use Type 1Power management capability structure 0x040 0x50MSI message capability structure 0x050 0x70PCI Express capability structure 0x070 0x000 (NULL)Advanced error reporting capabilitystructure0x100 0x148Secondary PCI Express capability structure 0x148 0x000 (NULL)PEX module internal configuration space 0x700 —BAR Mask Registers 0x1000 —Memory map/register overviewQorIQ LS1012A Reference Manual, Rev. 1, 01/20181244 NXP Semiconductors