NXP Semiconductors QorIQ LS1012A Reference Manual

32.6.14.2.4 Host system errorThe host controller is a bus master and any interaction between the host controller and thesystem may experience errors.The type of host error may be catastrophic to the host controller making it impossible forthe host controller to continue in a coherent fashion. Behavior for these types of errors isto halt the host controller. Host-based error must result in the following actions:• USBCMD[RS] is cleared.• USBSTS[SEI] and USBSTS[HCH] register are set• If the host system error enable bit, USBINTR[SEE] is set, the host controller issues ahardware interrupt. This interrupt is not delayed to the next interrupt threshold.The table below summarizes the required actions taken on the various host errors.Table 32-45. Summary behavior on host system errorsCycle type Master abort Target abort Data phase parityFrame list pointer fetch (read) Fatal Fatal FatalsiTD fetch (read) Fatal Fatal FatalsiTD status write-back (write) Fatal Fatal FataliTD fetch (read) Fatal Fatal FataliTD status write-back (write) Fatal Fatal FatalqTD fetch (read) Fatal Fatal FatalqHD status write-back (write) Fatal Fatal FatalData write Fatal Fatal FatalData read Fatal Fatal FatalNOTEAfter a host system error, software must reset the hostcontroller using USBCMD[RST] before re-initializing andrestarting the host controller.32.7 Device data structuresThis section defines the interface data structures used to communicate control, status, anddata between device controller driver (DCD) software and the device controller. The datastructure definitions in this chapter support a 32-bit memory buffer address space. Theinterface consists of device queue heads and transfer descriptors.Chapter 32 Universal Serial Bus Interface 2.0QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 2063