NXP Semiconductors QorIQ LS1012A Reference Manual

The TXRXS bit in the SR indicates the state of module. The bit is set if the module is inRunning state.The module starts or transitions to Running when all of the following conditions are true:• SR[EOQF] bit is clear• Chip is not in the Debug mode or the MCR[FRZ] bit is clear• MCR[HALT] bit is clearThe module stops or transitions from Running to Stopped after the current frame whenany one of the following conditions exist:• SR[EOQF] bit is set• Chip in the Debug mode and the MCR[FRZ] bit is set• MCR[HALT] bit is setState transitions from Running to Stopped occur on the next frame boundary if a transferis in progress, or immediately if no transfers are in progress.30.5.2 Serial Peripheral Interface (SPI) configurationThe SPI configuration transfers data serially using a shift register and a selection ofprogrammable transfer attributes. The module is in SPI configuration when the DCONFfield in the MCR is 0b00. The SPI frames can be 32 bits long. The host CPU or a DMAcontroller transfers the SPI data from the external to the module RAM queues to a TXFIFO buffer. The received data is stored in entries in the RX FIFO buffer. The host CPUor the DMA controller transfers the received data from the RX FIFO to memory externalto the module. The operation of FIFO buffers is described in the following sections:• Transmit First In First Out (TX FIFO) buffering mechanism• Command First In First Out (CMD FIFO) Buffering Mechanism• Receive First In First Out (RX FIFO) buffering mechanismThe interrupt and DMA request conditions are described in Interrupts/DMA requests.In Master mode the module initiates and controls the transfer according to the fields ofthe executing SPI Command.Chapter 30 Serial Peripheral Interface (SPI)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1837