NXP Semiconductors QorIQ LS1012A Reference Manual

1. Precharge all active banks (can be done through MDSCR) as requried by thestandard.2. Enter the DDR device into MPR mode through MRS/MRW commands.3. Configure the MMDC to work with MPR mode by assertingMPPDCMPR2[MPR_CMP].4. Make sure that the initial value that is configured in the read delay line absoluteoffset of each byte (MPRDDLCTL[RD_DL_ABS_OFFSET#]) will place the readDQS somewhere inside the read DQ window.5. Start the calibration process by asserting MPRDDLHWCTL[HW_RD_DL_EN].23.8.4.1.2 Hardware (automatic) Calibration with pre-defined valueIn case pre-defined mode is used, i.e. MPPDCMPR2[MPR_CMP] is cleared, then thefollowing steps should be executed:1. Precharge all active banks (Can be done through MDSCR) as required by thestandard.2. Configure the pre-defined value, which reflects the value that will be written andcompared through the read calibration, to MPPDCMPR1[PDV1, PDV2]3. Issue write access to the external DDR device by settingMPSWDAR0[SW_DUMMY_WR] = 1 (MMDC will generate internally write accesswithout intervention of the system towards bank 0, row 0, column 0)4. Make sure that the initial value that is configured in the read delay line absoluteoffset of each byte (i.e. MPRDDLCTL[RD_DL_ABS_OFFSET#] ) will place theread DQS somewhere inside the read DQ window5. Start the calibration process by asserting MPRDDLHWCTL[HW_RD_DL_EN]The following steps will be executed automatically by the MMDC for both modes(MPR and Pre-defined value):6. MMDC waits till the read delay-line is updated with the absolute delay value for allbytes at MPRDDLCTL[RD_DL_ABS_OFFSET#] and also satisfying the Tmod + 4requirement7. MMDC drives read command to the external DDR devices and waits 16 or 32 cycles(according to MPRDDLHWCTL[HW_RD_DL_CMP_CYC]) assuming that the datahas arrived from the DDR device.8. MMDC compares the read data byte to the associated byte in the pre-defined/MPRvalue for all the bytes in the DDR burst (burst length 4 or 8). If the comparison failsthen it indicates that the initial read DQS isn't inside the read DQ window and theMMDC generates an error for the associated byte atMPRDDLHWCTL[HW_RD_DL_ERR#] . If the comparison passes then MMDCadvances to next step.Chapter 23 Multi Mode DDR Controller (MMDC)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1111