NXP Semiconductors QorIQ LS1012A Reference Manual

• Unauthorized modifications to developer software and system configurationinformation (device trees, certificates). Protection consists of both prevention andafter the fact detection mechanisms• Unauthorized exposure of system persistent secrets. These are secrets that areintended to persist between resets of the system. The Trust Architecture persistentsecrets include the chip’s One Time Programmable Master Key (OTPMK), optionalZeroizable Master Key (ZMK), and any code, factory installed private asymmetric,and pre-shared symmetric keys encrypted by the OTPMK or ZMK and stored tononvolatile memory.• Unauthorized exposure of system ephemeral secrets. These are secrets that areintended to be cleared by the system’s next reset (or sooner). Trust architectureephemeral secrets include the chip’s Job Descriptor Key Encryption Keys (JDKEKs)and session keys negotiated during normal operation that are encrypted with aJDKEK (also known as, "Black Keys"). Secrets owned by the TEE and stored toSecure World private on-chip or off-chip private memory are also consideredephemeral.While some developers consider security policy enforcement to be a critical feature of thechip, other developers may not. Consequently the Trust Architecture is disabled bydefault. Developers not implementing trust features can ignore their existence.Developers who choose to leverage the Trust Architecture are not dependent on NXP toprovision chips or sign code. NXP is not part of the system development ormanufacturing chain of trust. Developer provisioning of chips is designed to be simple,with minimal impacts on manufacturing cycle times.29.5 Trust Architecture as implemented on the chip29.5.1 TrustZone (TZ) architecture in the Arm Cortex-coregeneral purpose processors (GPPs)The Arm GPPs support TrustZone in their CPU and cache architectures.Arm GPPs with Arm security extensions (TrustZone) have multiple execution modes asshown in the figure below,Trust Architecture as implemented on the chipQorIQ LS1012A Reference Manual, Rev. 1, 01/20181736 NXP Semiconductors