NXP Semiconductors QorIQ LS1012A Reference Manual

Field FunctionWrite leveling half cycle delay for Byte 1. This field indicates whether a delay of half cycle between CKand write DQS is added to the delay that is indicated in the associated WR_DL_ABS_OFFSET andWL_CYC_DEL. So the total delay is the sum of (WL_DL_ABS_OFFSET/256*cycle) + (WL_HC_DEL*halfcycle) + (WL_CYC_DEL*cycle).When SW write-leveling is enabled (i.e. SW_WL_EN = 1) then this value will be taken as is and will beadded to the associated delay that is configured in WL_DL_OFFSET and WL_CYC_DEL. When HWwrite-leveling is enabled (i.e. HW_WL_EN = 1 ) then this value will indicate (status) whether a delay ofhalf cycle was added or not to the associated WL_DL_OFFSET and WL_CYC_DEL.0b - No delay is added.1b - Half cycle delay is added.8—-Reserved9-15WL_DL_ABS_OFFSET1WL_DL_ABS_OFFSET1Absolute write-leveling delay offset for Byte 1. This field indicates the absolute delay between CK andwrite DQS of Byte1 with fractions of a clock period and up to half cycle. This value is process andfrequency independent. The value of the delay can be calculated using the following equation(WR_DL_ABS_OFFSET1 / 256) * clock periodWhen SW write-leveling is enabled (i.e. SW_WL_EN = 1) then this value will be taken as is to theassociated delay-line. When HW write-leveling is enabled (i.e. HW_WL_EN = 1 ) then this value willindicate (status) the value that is taken to the associated delay-line at the end of the write-levelingcalibration.NOTE: The delay-line has a resolution that may vary between device to device, therefore is some casesan increment of the delay by 1 step may be smaller than the delay-line resolution.16-20—-Reserved21-22WL_CYC_DEL0WL_CYC_DEL0Write leveling cycle delay for Byte 0. This field indicates whether a delay of 1 or 2 cycles between CK andwrite DQS is added to the delay that is indicated in the associated WR_DL_ABS_OFFSET andWL_HC_DEL. So the total delay is the sum of (WL_DL_ABS_OFFSET/256*cycle) + (WL_HC_DEL*halfcycle) + (WL_CYC_DEL*cycle).When both SW write-leveling is enabled (i.e. SW_WL_EN = 1) or HW write-leveling is enabled (i.e.HW_WL_EN = 1 ) then this value will be taken as is and will be added to the associated delay that isconfigured in WL_DL_OFFSET and WL_HC_DEL.Note that in HW write-leveling this field is not used for indication, as in WL_DL_OFFSET andWL_HC_DEL, but for configuration.00b - No delay is added.01b - 1 cycle delay is added.10b - 2 cycles delay is added.11b - Reserved.23WL_HC_DEL0WL_HC_DEL0Write leveling half cycle delay for Byte 0. This field indicates whether a delay of half cycle between CKand write DQS is added to the delay that is indicated in the associated WR_DL_ABS_OFFSET andWL_CYC_DEL. So the total delay is the sum of (WL_DL_ABS_OFFSET/256*cycle) + (WL_HC_DEL*halfcycle) + (WL_CYC_DEL*cycle).When SW write-leveling is enabled (i.e. SW_WL_EN = 1) then this value will be taken as is and will beadded to the associated delay that is configured in WL_DL_OFFSET and WL_CYC_DEL. When HWwrite-leveling is enabled (i.e. HW_WL_EN = 1 ) then this value will indicate (status) whether a delay ofhalf cycle was added or not to the associated WL_DL_OFFSET and WL_CYC_DEL.Table continues on the next page...Chapter 23 Multi Mode DDR Controller (MMDC)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1173