NXP Semiconductors QorIQ LS1012A Reference Manual

• SGMII notation for PFE:• sg.mn means SGMII (1 lane @ 1.25 GBaud or 3.125 GBaud)• "m" indicates that MAC is from PFE.• "n" indicates which MAC on the PFE.• For example, "sg.m2," indicates SGMII for MAC 2 on PFE.• PCI Express :• PEXn (5/2.5) means PCI Express operating up to 5 or 2.5 GT/s depending onmaximum rate selection and training.• SATA• SATAn (6/3/1.5) means SATA operating at 6 or 3 or 1.5 Gbps depending on rateselection. The rate of selection is performed by PxSCTL[SPD] register asdescribed in SATA 3.0.Table 28-1. Lane assignments for SerDesSerDes Lane A B C DSignal SD1_RX0_P/SD1_RX0_N/SD1_TX0_P/SD1_TX0_NSD1_RX1_P/SD1_RX1_N/SD1_TX1_P/SD1_TX1_NUnused SD1_RX2_P/SD1_RX2_N/SD1_TX2_P/SD1_TX2_NController LaneAssignments- PCI Express (x1) PCI Express (x1)TX_CLK TX_CLK -- - SATA 1sg.m1 (1G/2.5G) sg.m2 (1G/2.5G) -NOTEThe names of lanes A, B, C, and D are interchangeably usedwith 0, 1, 2, and 3 respectively.The following table shows the supported networking protocol options for the SerDesmodule. The SerDes protocols are configured through software and not at power-on-reset.The SerDes lane A and lane B for SGMII are driven by MAC1 and MAC2, respectively.However, the RGMII interface is driven by Ethernet MAC2 of PFE. If SerDes isconfigured for two SGMII interfaces, the RGMII interface is not used. If only the SerDeslane A is used for SGMII, RGMII is available at MAC2.The two lanes of SGMII are completely independent. The MAC connected to the SerDeslane B is the same MAC connected to the RGMII interface. The only exception to theSerDes lane being selected independently is that PCI Express is only supported on oneSerDes lane and cannot be enabled at two lanes simultaneously.The SerDes module as implemented on the chipQorIQ LS1012A Reference Manual, Rev. 1, 01/20181592 NXP Semiconductors