NXP Semiconductors QorIQ LS1012A Reference Manual

By programming the lockdown_select, and lockdown_range registers, and asserting thesecure_boot_lock signal, you can lockdown the behavior of the TZASC so that itprevents unintentional or erroneous write to the regions specified in the lockdown_rangeRegister. However, read access to those regions is permitted:• region_setup_low_ Register. See Region Setup Low 0 Register (region_setup_low_0)• region_setup_high_ Register. See Region Setup High 0 Register (region_setup_high_0)• region_attributes_ Register. See Region Attributes 0 Register (region_attributes_0).The TZASC expects the secure_boot_lock signal to be asserted for at least one clockcycle. One clock after the secure_boot_lock is sampled HIGH by TZASC, then theregisters mentioned in Locking down the region using lockdown_range andlockdown_select registers cannot be written, unless the TZASC is reset by assertingaresetn.10.4.1.9 Using locked transaction sequencesIf a master performs locked transaction sequences, a transaction might stall, or an AXIprotocol violation might occur when:Transaction sequence crosses a 4 KB boundaryIf a locked transaction sequence crosses a 4 KB boundary and the regions have differentregion permissions, the TZASC might prevent access to the second region and thereforethe slave would not receive the latter part of the locked transaction sequence.NOTEThe AXI protocol recommends that locked transactionsequences do not cross a 4 KB address boundary.Secure state changeDuring a locked transaction sequence, if a master changes the state of secure and non-secure attributes and the region has different region permissions for Secure state andNon-secure state, the TZASC might deny a transaction and therefore the slave would notreceive the latter part of the locked transaction sequence.Reads and writesChapter 10 Arm CoreLink™ TrustZone Address Space Controller TZC-380QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 467