NXP Semiconductors QorIQ LS1012A Reference Manual

NOTEAfter receiving a new setup packet the status and/or handshakephases may still be pending from a previous control sequence.These should be flushed and de-allocated before linking a newstatus and/or handshake dTD for the most recent setup packet.32.8.3.5.2 Data phaseIf the control transfer requires a data stage following the setup phase, the DCD mustcreate a device transfer descriptor for the data phase and prime the transfer.After priming the packet, the DCD must verify a new setup packet has not been receivedby reading the ENDPTSETUPSTAT register immediately verifying that the prime hadcompleted. A prime will complete when the associated bit in the ENDPTPRIME registeris zero and the associated bit in the ENDPTSTATUS register is a one. If a prime fails,that is, The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit is not set, thenthe prime has failed. This can only be due to improper setup of the dQH, dTD or a setuparriving during the prime operation. If a new setup packet is indicated after theENDPTPRIME bit is cleared, then the transfer descriptor can be freed and the DCD mustreinterpret the setup packet.Should a setup arrive after the data stage is primed, the device controller willautomatically clear the prime status (ENDPTSTATUS) to enforce data coherency withthe setup packet.NOTEThe MULT field in the dQH must be set to '00' for bulk,interrupt, and control endpoints.NOTEError handling of data phase packets is the same as bulk packetsdescribed previously.32.8.3.5.3 Status phaseSimilar to the data phase, the DCD must create a transfer descriptor (with byte lengthequal zero) and prime the endpoint for the status phase.The DCD must also perform the same checks of the ENDPTSETUPSTAT as describedabove in the data phase.NOTEThe MULT field in the dQH must be set to '00' for bulk,interrupt, and control endpoints.Chapter 32 Universal Serial Bus Interface 2.0QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 2083