NXP Semiconductors QorIQ LS1012A Reference Manual

Offset Register Width(In bits)Access Reset value10h MMDC Core Timing Configuration Register 1 (MDCFG1) 32 RW B6B1_8A23h14h MMDC Core Timing Configuration Register 2 (MDCFG2) 32 RW 00C7_0092h18h MMDC Core Miscellaneous Register (MDMISC) 32 RW 0000_1600h1Ch MMDC Core Special Command Register (MDSCR) 32 RW 0000_0000h20h MMDC Core Refresh Control Register (MDREF) 32 RW 0000_C000h2Ch MMDC Core Read/Write Command Delay Register (MDRWD) 32 RW 0F9F_26D2h30h MMDC Core Out of Reset Delays Register (MDOR) 32 RW 009F_0E0Eh400h MMDC Core AXI Reordering Control Register (MAARCR) 32 RW 5142_01F0h404h MMDC Core Power Saving Control and Status Register (MAPSR) 32 RW 0000_1007h408h MMDC Core Exclusive ID Monitor Register0 (MAEXIDR0) 32 RW 0020_0000h40Ch MMDC Core Exclusive ID Monitor Register1 (MAEXIDR1) 32 RW 0060_0040h410h MMDC Core Debug and Profiling Control Register 0 (MADPCR0) 32 RW 0000_0000h414h MMDC Core Debug and Profiling Control Register 1 (MADPCR1) 32 RW 0000_0000h418h MMDC Core Debug and Profiling Status Register 0 (MADPSR0) 32 RO 0000_0000h41Ch MMDC Core Debug and Profiling Status Register 1 (MADPSR1) 32 RO 0000_0000h420h MMDC Core Debug and Profiling Status Register 2 (MADPSR2) 32 RO 0000_0000h424h MMDC Core Debug and Profiling Status Register 3 (MADPSR3) 32 RO 0000_0000h428h MMDC Core Debug and Profiling Status Register 4 (MADPSR4) 32 RO 0000_0000h42Ch MMDC Core Debug and Profiling Status Register 5 (MADPSR5) 32 RO 0000_0000h430h MMDC Core Step By Step Address Register (MASBS0) 32 RO 0000_0000h434h MMDC Core Step By Step Address Attributes Register (MASBS1) 32 RO 0000_0000h440h MMDC Core General Purpose Register (MAGENP) 32 RW 0000_0000h800h MMDC PHY ZQ HW control register (MPZQHWCTRL) 32 RW A138_0000h804h MMDC PHY ZQ SW control register (MPZQSWCTRL) 32 RW 0000_0000h808h MMDC PHY Write Leveling Configuration and Error Status Register(MPWLGCR)32 RW 0000_0000h80Ch MMDC PHY Write Leveling Delay Control Register 0 (MPWLDECTRL0)32 RW 0000_0000h814h MMDC PHY Write Leveling delay-line Status Register (MPWLDLST) 32 RO 0000_0000h818h MMDC PHY ODT control register (MPODTCTRL) 32 RW 0000_0000h81Ch MMDC PHY Read DQ Byte0 Delay Register (MPRDDQBY0DL) 32 RW 0000_0000h820h MMDC PHY Read DQ Byte1 Delay Register (MPRDDQBY1DL) 32 RW 0000_0000h82Ch MMDC PHY Write DQ Byte0 Delay Register (MPWRDQBY0DL) 32 RW 0000_0000h830h MMDC PHY Write DQ Byte1 Delay Register (MPWRDQBY1DL) 32 RW 0000_0000h83Ch MMDC PHY Read DQS Gating Control Register 0 (MPDGCTRL0) 32 RW 0000_0000h844h MMDC PHY Read DQS Gating delay-line Status Register (MPDGDLST0)32 RO 0000_0000h848h MMDC PHY Read delay-lines Configuration Register (MPRDDLCTL) 32 RW 4040_4040h84Ch MMDC PHY Read delay-lines Status Register (MPRDDLST) 32 RO 0000_0000h850h MMDC PHY Write delay-lines Configuration Register (MPWRDLCTL) 32 RW 4040_4040hTable continues on the next page...Chapter 23 Multi Mode DDR Controller (MMDC)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1123