NXP Semiconductors QorIQ LS1012A Reference Manual

Section number Title Page28.5.17.3 Diagram......................................................................................................................................162828.5.17.4 Fields.......................................................................................................................................... 162828.5.18 Receive Equalization Control Register 1- Lane a (LNARECR1 - LNDRECR1)..........................................163028.5.18.1 Offset..........................................................................................................................................163128.5.18.2 Function..................................................................................................................................... 163128.5.18.3 Diagram......................................................................................................................................163128.5.18.4 Fields.......................................................................................................................................... 163128.5.19 Transmit Equalization Control Register 0 - Lane a (LNATECR0 - LNDTECR0)....................................... 163228.5.19.1 Offset..........................................................................................................................................163228.5.19.2 Function..................................................................................................................................... 163228.5.19.3 Diagram......................................................................................................................................163228.5.19.4 Fields.......................................................................................................................................... 163328.5.20 Speed Switch Control Register 1- Lane 0 (LNASSCR1 - LNDSSCR1)....................................................... 163428.5.20.1 Offset..........................................................................................................................................163528.5.20.2 Function..................................................................................................................................... 163528.5.20.3 Diagram......................................................................................................................................163528.5.20.4 Fields.......................................................................................................................................... 163528.5.21 TTL Control Register 0 - Lane a (LNATTLCR0 - LNDTTLCR0)............................................................... 163828.5.21.1 Offset..........................................................................................................................................163828.5.21.2 Function..................................................................................................................................... 163928.5.21.3 Diagram......................................................................................................................................163928.5.21.4 Fields.......................................................................................................................................... 163928.5.22 Test Control/Status Register 3 - Lane a (LNATCSR3 - LNDTCSR3)..........................................................164028.5.22.1 Offset..........................................................................................................................................164028.5.22.2 Function..................................................................................................................................... 164028.5.22.3 Diagram......................................................................................................................................164028.5.22.4 Fields.......................................................................................................................................... 164028.5.23 PEXA Protocol Control Register 0 (PEXACR0)...........................................................................................164128.5.23.1 Offset..........................................................................................................................................1641QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 115