NXP Semiconductors QorIQ LS1012A Reference Manual

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RDOZEMDIS Reserved0 0ReservedReservedReservedReservedReservedReservedEND_CFGSWRSTHDSWRSTSDWCLR_TXFCLR_RXFReset 0 1 0 0 0 0 0 0 0 0 0 0 * * 0 0* Notes:END_CFG field: See the module configuration for the device specific reset value.•QuadSPI_MCR field descriptionsField Description31–24SCLKCFGSerial Clock Configuration. This field configuration is chip specific. For details, refer to chip-specificQuadSPI information. It may be used for dividing clocks.23–20ReservedThis field is reserved.19–16ReservedThis field is reserved.This field is reserved and should always be set to 0xF.15DOZEDoze Enable. The DOZE bit provides support for externally controlled Doze Mode power-savingmechanism.0 A doze request will be ignored by the QuadSPI module1 A doze request will be processed by the QuadSPI module14MDISModule Disable. The MDIS bit allows the clock to the non-memory mapped logic in the QuadSPI to bestopped, putting the QuadSPI in a software controlled power-saving state.0 Enable QuadSPI clocks.1 Allow external logic to disable QuadSPI clocks.13–12ReservedThis field is reserved.11CLR_TXFClear TX FIFO/Buffer. Invalidates the TX Buffer content.This is a self-clearing field.0 No action.1 Read and write pointers of the TX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0.Table continues on the next page...Chapter 26 Quad Serial Peripheral Interface (QuadSPI)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1441