NXP Semiconductors QorIQ LS1012A Reference Manual

27.3.8.4 FieldsField Function31ESDFEnable signal detect filterWhen set, a single de-assertion of signal detect or the coreRxDataValid, when the PHY Init state machineis in the PHYReady state, causes the state machine to exit the PHYReady state and return to aPhyNotReady state. This results in the OOB and speed negotiation running again.30ERSNEnable reset speed negotiationWhen set, the PHY control layer enables only a single speed on the RX path during speed negotiation.This speed is determined as the fastest support for the first round falling to the lowest speed for the finalround. Each round of speed negotiation is terminated by the host issuing a COMRESET and rerunningOOB before beginning the next round of speed negotiation as detailed in reset speed negotiation (RSN).29PSSPhyControl SerDes slumberThis bit selects SerDes slumber CMU during link slumber. When this bit is set and the controller entersslumber, an extra control signal is applied to the SerDes to slumber the clock block within SerDes. Thisyields an extra power savings that is SerDes specific.28PSSOPhyControl select SerDes OOBThis bit selects SerDes OOB or internally decoded OOB signalling as input.0b - Select SerDes decoded OOB signalling1b - Select internally decoded OOB signalling27STBStatus bitThis bit provides the status of the Gen fixed clocks parameter. This bit indicates if the PHY control layer isrunning from a fixed frequency clock or a variable clock derived from the TX clock of the SerDes.26PBPNAPhyControl BIST pattern no alignsSetting this bit causes the PHY control pattern generator to transmit each pattern continuously.25PBCEPhyControl BIST clear errorWhen a pattern mismatch occurs, this bit needs to be set and then negated to clear the error.0b - Pattern match error bit is not cleared1b - Clears the pattern match error bit24PBPEPhyControl BIST pattern enableThis bit controls enabling/disabling the PHY control test pattern generation. For more information, refer toPhyControl BIST modes0b - Disables the PHY control test pattern generation1b - Enables the PHY control test pattern generation23-21PBPSPhyControl BIST pattern selectThe settings not defined below are reserved.000b - LBP (generator clock only)001b - LFTP010b - MFTP011b - HFTP100b - PRBS pattern101b - BIST pattern (default)20FPRForce PHY ReadyThis bit determines how PHY Ready is driven.0b - Normal operation mode1b - FrcPhyRdy: In this mode, the OOB and speed negotiation states of the PHY Init state machineare bypassed. The PHY Init state machine directly enters PHY Ready after reset. The Tx bufferIDLE control is forced off.Table continues on the next page...Chapter 27 SATA 3.0QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1529