NXP Semiconductors QorIQ LS1012A Reference Manual

"Wakeup Logic" module implements SRP detection in A-Device mode. This is requiredif the USB 3.0 controller is powered down completely while ADP is still in progress andB-Device initiates SRP.NOTEADP controller logic is inferred along with, but outside USB3.0 controller.• As a product, both ADP controller logic and OTGcontroller are packaged into USB 3.0 core.• All ADP timers are maintained in the ADP controllermodule, which generates the enable and disable signalingto the PHY for ADP probing and sensing.• PHY contains the following circuitry related to ADPfunctionality:• Comparators for PRB and SNS• I_ADP_SRC and I_ADP_SNK• VBUS circuitry• Application software programs the ADP timing registersthat resides in the pwrm_otgif module.• The pwrm_otgif module provides a mechanism to theapplication via interrupts to log and report events pertainingto ADP probing and sensing.• In this operation, only the pwrm module needs to be alwayspowered on. The pwrdwn module can be either powered onor off.33.4.7 Initialization/application informationThe PHY can be configured for fixed equalization by programming relevant controlregisters in the USB 3.0 PHY.In order to initialize the USB 3.0 PHY, software should perform the following steps:1. Write 1'b0 to RX_OVRD_IN_HI.RX_EQ_EN [address 16'h1006: bit 6].2. Write 1'b1 to RX_OVRD_IN_HI.RX_EQ_EN_OVRD [address 16'h1006: bit 7].3. Write a fixed value to RX_OVRD_IN_HI.RX_EQ [address 16'h1006: bits 10–8][equalization setting] (generally 2–4, based on testing in customer environment).4. Write 1'b1 to RX_OVRD_IN_HI.RX_EQ_OVRD [address 16'h1006: bit 11].Chapter 33 Universal Serial Bus Interface 3.0QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 2329