NXP Semiconductors QorIQ LS1012A Reference Manual

Note that the controller splits transactions at the crossing of every 256-byte-alignedboundary when sending data back to the PCI Express link.25.2.2 FeaturesThe following is a list of features supported by the PCI Express controller:• Compatible with the PCI Express™ Base Specification, Revision 3.0• Supports Root Complex (RC) and Endpoint (EP) configurations• 32- and 64-bit PCI Express address support• 40-bit internal platform address support• x1 link support.• Supports accesses to all PCI Express memory and I/O address spaces (requestoronly)• Supports posting of processor-to-PCI Express and PCI Express-to-memory writes• Supports strong and relaxed transaction ordering rules• Enforces outbound PCI Express ordering rules and inbound internal platform priority• PCI Express configuration registers (type 0 in EP mode, type 1 in RC mode)• Baseline and advanced error reporting support• One virtual channel (VC0)• 256-byte maximum payload size (MAX_PAYLOAD_SIZE)• Supports 64-bit MSI interrupts. Note that MSI support is provided in the SCFGmodule.• Credit-based flow control management handled by PCI Express core.• Supports PCI Express messages and interrupts• Accepts up to 256-byte transactions from the internal platform• Supports Expansion ROM.25.2.3 Modes of OperationSeveral parameters that affect the PCI Express controller modes of operation aredetermined at power-on reset (POR) by reset configuration word (RCW) fieldsconfigured depending on SoC product.Table 25-1. POR Parameters for PCI Express ControllerRCW Parameter DescriptionHost/Agent Selects between Root Complex (RC) and Endpoint (EP) modesSerDes Protocol SelectSRDS_PRTCL_SnDetermines the link widthTable continues on the next page...IntroductionQorIQ LS1012A Reference Manual, Rev. 1, 01/20181242 NXP Semiconductors