NXP Semiconductors QorIQ LS1012A Reference Manual

7. If the host polls the endpoint prior to the time specified in the Start Transfercommand, the hardware will respond with a zero-length packet and no interrupt willbe made to software.8. If the host polls the endpoint during the expected interval and the hardware has nodata prepared, the core will respond with a zero-length packet, but no XferNotReadyevent will be generated because the transfer is active. When the next interval starts,the XferInProgress event is generated (based on ISP and IMI) with the "MissedIsochronous" status, which is the way software finds out that this occurred.For OUT endpoints, the hardware performs the following functions:1. If a packet is received for the correct interval represented by the Buffer Descriptor(call it A).a. Write the packet into the buffer.b. Decrement the buffer size of the TRB.c. Write the timestamp of the received packet into the TRB.d. Retire a TRB when its buffer size reaches 0, issuing an XferInProgress event ifthe IOC bit is set.2. If a short packet or packet with the last packet flag (lpf) is received for the correctinterval.a. Write the packet into the buffer.b. Retire the Buffer Descriptor of interval A with the TRBSTS set to 0.c. If the IOC bit is set in the last TRB of the Buffer Descriptor, issue anXferInProgress event with bit [13] set.d. Go to step 1 to prepare for interval B.3. If a packet is received for the correct interval but it has an error (CRC error, RXFIFOoverflow), the core will not increment its expected sequence number value whichcauses future packets within the same interval to be dropped.4. If a packet is received at a bus time prior to the time specified in the Start Transfercommand, it will be dropped.5. If a packet is received for the correct interval (A), but not enough buffer space isavailable for the core to write the packet (due to the HWO bit still '0' in one or moreof the TRBs of the Buffer Descriptor), no XferNotReady event will be generated.The core will behave as follows:a. Wait until software sets the HWO bit to '1' and issues an Update Transfercommandb. Retire the Buffer Descriptor of interval A with a "Missed Isochronous" statusc. Go to step 1 to prepare for interval B.6. If a packet is received for the next interval (B) before all the packets have beenreceived for interval A:a. Retire the Buffer Descriptor of interval A with a "Missed Isochronous" status.b. Retire the Buffer Descriptor of interval B with a "Missed Isochronous" status.Functional DescriptionQorIQ LS1012A Reference Manual, Rev. 1, 01/20182274 NXP Semiconductors