NXP Semiconductors QorIQ LS1012A Reference Manual

Table 28-6. Clause 22 registersRegisters Notes SeeSGMII MDIO_SGMII register descriptionsNOTEThroughout the MDIO register sections:• Each MDIO register is 16 bits.• Register offsets are 16-bit offsets, not byte offsets.• Addresses not listed are reserved.• Read accesses to reserved addresses return 0x0000.28.6.1 MDIO_KX_PCS register descriptionsThe 1000Base-KX PCS register space is selected when the associatedSGMIInCR1[MDEV_PORT] matches the Ethernet MAC port address(MDIO_CTL[PORT_ADDR]) and the device address (MDIO_CTL[DEV_ADDR]) is03h.This register space is also used for (vendor-specific) Clause 45 access to SGMII registeraliases (starting at register address 8000h).28.6.1.1 MDIO_KX_PCS Memory mapMDIO_KX_PCS base address: 0hOffset Register Width(In bits)Access Reset value0h KX PCS Control (KX_PCS_CR) 16 RW 1140h1h KX PCS Status (KX_PCS_SR) 16 RO 0009h2h KX PCS Device Identifier Upper (KX_PCS_DEV_ID) 16 RO 0083h3h KX PCS Device Identifier Lower (KX_PCS_DEV_ID_L) 16 RO E400h5h KX PCS Devices In Package 0 (KX_PCS_DEV_PRES0) 16 RO 0000h6h KX PCS Devices In Package 1 (KX_PCS_DEV_PRES1) 16 RO 0088hEh KX PCS Package Identifier Upper (KX_PCS_PKG_ID_U) 16 RO 0083hFh KX PCS Package Identifier Lower (KX_PCS_PKG_ID_L) 16 RO E400h8000h SGMII Control (C45_SGMII_CR) 16 RW 1140h8001h SGMII Status (C45_SGMII_SR) 16 RO 0009hTable continues on the next page...MDIO register spacesQorIQ LS1012A Reference Manual, Rev. 1, 01/20181646 NXP Semiconductors