NXP Semiconductors QorIQ LS1012A Reference Manual

Note that some clock signals are specific to modules within the chip, and although someof their functionality is described here, they are defined in detail in their respectivechapters.Table 4-4. Clock External Signals-Detailed Signal DescriptionsSignal I/O DescriptionSD_REF_CLKn_P,SD_REF_CLKn_NI SerDes high-speed interface differential reference clocks. These differential clockinputs are used to independently clock the banks/ports of high-speed differentialsignal lanes available on the chip. The SerDes reference clock timing specificationsare given in the chip data sheet . See the Reference Clocks for SerDes Protocolssection in the SerDes Module chapter.NOTE: The SerDes clock is internally generated and the external clock is analternate source.Timing Assertion/Negation-See the chip data sheet for specific timinginformation for these signals.CLK_OUT O Diagnostic clock output. This output may be configured to offer one of a variety ofinternal system clocks to external hardware for diagnostic or debug purposes. SeeCLK_OUT configuration.4.3 Clocking register descriptionsThe following table summarizes the memory mapped registers which are used toconfigure clocking features.4.3.1 Clocking Memory mapClocking base address: 1EE_1000hOffset Register Width(In bits)Access Reset value0h Core cluster n clock control/status register (CLKC1CSR) 32 RW 0000_0000h800h PLL cluster n general status register (PLLC1GSR) 32 RW 0000_0000hA00h Platform clock domain control/status register (CLKPCSR) 32 RW 0000_0000hC00h Platform PLL general status register (PLLPGSR) 32 RO 0000_0000h4.3.2 Core cluster n clock control/status register (CLKC1CSR)Clocking register descriptionsQorIQ LS1012A Reference Manual, Rev. 1, 01/2018224 NXP Semiconductors