NXP Semiconductors QorIQ LS1012A Reference Manual

19.5.10.1 CNTIN register updateThe following table describes when CNTIN register is updated:Table 19-9. CNTIN register updateWhen Then CNTIN register is updatedCLKS[1:0] = 0:0 When CNTIN register is written, independent of FTMEN bit.• FTMEN = 0, or• CNTINC = 0At the next system clock after CNTIN was written.• FTMEN = 1,• SYNCMODE = 1, and• CNTINC = 1By the CNTIN register synchronization.19.5.10.2 MOD register updateThe following table describes when MOD register is updated:Table 19-10. MOD register updateWhen Then MOD register is updatedCLKS[1:0] = 0:0 When MOD register is written, independent of FTMEN bit.• CLKS[1:0] ≠ 0:0, and• FTMEN = 0According to the CPWMS bit, that is:• If the selected mode is not CPWM then MOD register is updated after MODregister was written and the FTM counter changes from MOD to CNTIN. Ifthe FTM counter is at free-running counter mode then this update occurswhen the FTM counter changes from 0xFFFF to 0x0000.• If the selected mode is CPWM then MOD register is updated after MODregister was written and the FTM counter changes from MOD to (MOD –0x0001).• CLKS[1:0] ≠ 0:0, and• FTMEN = 1By the MOD register synchronization.19.5.10.3 CnV register updateThe following table describes when CnV register is updated:Table 19-11. CnV register updateWhen Then CnV register is updatedCLKS[1:0] = 0:0 When CnV register is written, independent of FTMEN bit.• CLKS[1:0] ≠ 0:0, and• FTMEN = 0According to the selected mode, that is:Table continues on the next page...Chapter 19 FlexTimer Module (FTM)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 933