NXP Semiconductors QorIQ LS1012A Reference Manual

Table 4-10. RCW Field Descriptions (continued)Bit(s) (of0-511)Field Name Description Notes/commentsRESET_REQ_B in both the RCW fieldssimultaneously is prohibited.• Refer Differences between siliconrevisions 1.0 and 2.0 for theimplementation in silicon revision 1.0.GROUP B PIN CONFIGURATION (BITS 384-415)384-415 Reserved. Must be set to all 0's.SoC-SPECIFIC CONFIGURATION (BITS 416-447)416-418 Reserved. Must be set to 00.419 SDHC1_CD This field selects thefunctionality assigned to theSDHC1_CD_B pin.Options:0 GPIO1[21]1 SDHC1_CD_B420 SDHC1_WP This field selects thefunctionality assigned to theSDHC1_WP pin.Options:0 GPIO1[22]1 SDHC1_WP421 QSPI_DATA0_GPIO This field selects thefunctionality of the QSPI pinsfor 2-bit interface.Options:0 QSPI_A_DATA0, QSPI_A_SCK, QSPI_A_CS01 GPIO1[11], GPIO1[4], GPIO1[5]422-423 QSPI_DATA1_GPIO This field selects thefunctionality of the QSPI pinsfor 2-bit interface.Options:00 QSPI_A_DATA101 GPIO1[12]10 Reserved11 Reserved424-425 QSPI_IIC2 This field selects thefunctionality of the QuadSPIpins for additional data bits forthe 4-bit interface.Options:00 GPIO1[13], GPIO1[14]01 IIC2_SCL, IIC2_SDA10 QSPI_A_DATA2, QSPI_A_DATA311 GPIO1[13], RESET_REQ_BNOTE: • The QuadSPI multiplexing can bechanged by software throughSCFG_PMUXCR0 register.• RESET_REQ_B is selected througheither RCW[382:383] orRCW[QSPI_IIC2]. Selection ofRESET_REQ_B in both the RCW fieldssimultaneously is prohibited.• Refer Differences between siliconrevisions 1.0 and 2.0 for theimplementation in silicon revision 1.0.426-428 Reserved. Must be set to all 0's.429-430 USB1_DRVVBUS_BASEThis field configures thefunctionality of theUSB1_DRVVBUS pin.Options:00 GPIO2[0]Table continues on the next page...Chapter 4 Reset, Clocking, and InitializationQorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 243