NXP Semiconductors QorIQ LS1012A Reference Manual

complete condition is indicated by both bits reading zero after the TCDn_CSR[START]was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the activestatus may be missed if the channel execution is short in duration.The TCD status bits execute the following sequence for a software activated channel:Stage TCDn_CSR bits StateSTART ACTIVE DONE1 1 0 0 Channel service request via software2 0 1 0 Channel is executing3a 0 0 0 Channel has completed the minor loop and is idle3b 0 0 1 Channel has completed the major loop and is idleThe best method to test for minor-loop completion when using hardware, that is,peripheral, initiated service requests is to read the TCDn_CITER field and test for achange. The hardware request and acknowledge handshake signals are not visible in theprogrammer's model.The TCD status bits execute the following sequence for a hardware-activated channel:Stage TCDn_CSR bits StateSTART ACTIVE DONE1 0 0 0 Channel service request via hardware (peripheralrequest asserted)2 0 1 0 Channel is executing3a 0 0 0 Channel has completed the minor loop and is idle3b 0 0 1 Channel has completed the major loop and is idleFor both activation types, the major-loop-complete status is explicitly indicated via theTCDn_CSR[DONE] bit.The TCDn_CSR[START] bit is cleared automatically when the channel begins executionregardless of how the channel activates.17.6.5.2 Reading the transfer descriptors of active channelsThe eDMA reads back the true TCDn_SADDR, TCDn_DADDR, and TCDn_NBYTESvalues if read while a channel executes. The true values of the SADDR, DADDR, andNBYTES are the values the eDMA engine currently uses in its internal register file andnot the values in the TCD local memory for that channel. The addresses, SADDR andInitialization/application informationQorIQ LS1012A Reference Manual, Rev. 1, 01/2018714 NXP Semiconductors