NXP Semiconductors QorIQ LS1012A Reference Manual

23.9.1.42.3 DiagramBits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15R0ReservedReservedReservedWReset 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31R 0 WR_DL_ABS_OFFSET1 0 WR_DL_ABS_OFFSET0WReset 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 023.9.1.42.4 FieldsField Function0—-Reserved1-7—-Reserved8—-Reserved9-15—-Reserved16—-Reserved17-23WR_DL_ABS_OFFSET1WR_DL_ABS_OFFSET1Absolute write delay offset for Byte1. This field indicates the absolute delay between write DQS strobeand the write data of Byte1 with fractions of a clock period and up to half cycle. The fraction is processand frequency independent. The delay of the delay-line would be (WR_DL_ABS_OFFSET1 / 256) *MMDC AXI clock (fast clock). So for the default value of 64, a quarter cycle delay is found.This field can also bit written by HW. Upon completion of the write delay-line HW calibration this field getsthe value of (HW_WR_DL_LOW1 + HW_WR_DL_UP1) /2Note that not all changes of this value will affect the actual delay. If the requested change is smaller thanthe delay-line resolution, then no change will occur.24—-Reserved25-31WR_DL_ABS_OFFSET0WR_DL_ABS_OFFSET0Absolute write delay offset for Byte0. This field indicates the absolute delay between write DQS strobeand the write data of Byte3 with fractions of a clock period and up to half cycle. The fraction is processand frequency independent. The delay of the delay-line would be (WR_DL_ABS_OFFSET0 / 256) *MMDC AXI clock (fast clock). So for the default value of 64, a quarter cycle delay is found.Chapter 23 Multi Mode DDR Controller (MMDC)QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1197