NXP Semiconductors QorIQ LS1012A Reference Manual

For information on device queue heads, refer to Device data structures.5. Configure the ENDPOINTLISTADDR pointer.For additional information on ENDPOINTLISTADDR, refer to the register table.6. Enable the microprocessor interrupt associated with the USB DR module andoptionally change setting of USBCMD[ITC].Recommended: enable all device interrupts including: USBINT, USBERRINT, PortChange Detect, USB Reset Received, DCSuspend.For a list of available interrupts refer to the USBINTR and the USBSTS registertables.7. Set USBCMD[RS] to run mode.After the run bit is set, a device reset will occur. The DCD must monitor the resetevent and set the DEVICEADDR register, set the ENDPTCTRLx registers, andadjust the software state as described in Bus reset.NOTEEndpoint 0 is designed as a control endpoint only and does notneed to be configured using ENDPTCTRL0 register.It is also not necessary to initially prime Endpoint 0 because the first packet received willalways be a setup packet. The contents of the first setup packet will require a response inaccordance with USB device framework command set.32.8.2 Port state and controlFrom a chip or system reset, the USB_DR controller enters the powered state.A transition from the powered state to the attach state occurs when the run/stop bit(USBCMD[RS]) is set to a '1'. After receiving a reset on the bus, the port will enter thedefaultFS or defaultHS state in accordance with the protocol reset described in AppendixC.2 of the USB Specification Rev. 2.0. The figure below depicts the state of a USB 2.0device.Chapter 32 Universal Serial Bus Interface 2.0QorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 2071