NXP Semiconductors QorIQ LS1012A Reference Manual

2. Setup the Region Base and Limit Address Registers.Write 0x00010000 to Address {0x700 + 0x20C} to set the Lower Base Address.Write 0x00000000 to Address {0x700 + 0x210} to set the Upper Base Address.Write 0x0005ffff to Address {0x700 + 0x214} to set the Limit Address3. Setup the Target Address Registers.Write 0x20000000 to Address {0x700 + 0x218} to set the Lower Target Address.Write 0x10000000 to Address {0x700 + 0x21C} to set the Upper Target Address.4. Configure the region through the Region Control 1 Register.Write 0x00000000 to Address {0x700 + 0x204} to define the type of the region to beMEM.5. Enable the region.Write 0x80000000 to Address {0x700 + 0x208} to enable the region in addressmatch mode.NOTE• EP port: Defined MEM regions must be inside an enabledBAR range.• RC port: Defined MEM regions must either match a BARor be outside of the base and limit ranges defined for theport in the Type 1 configuration header.25.6.1.4 Memory Space AddressingA PCI Express memory transaction can address a 32- or 64-bit memory space. As aninitiator, the controller is capable of sending 32- or 64-bit memory packets. Anytransaction from the internal platform that (after passing through the translationmechanism) has a translated address greater than 4G is sent as a 64-bit memory packet.Otherwise, a 32-bit memory packet is sent. As a target device, the controller is capable ofdecoding 32- or 64-bit memory packets. This is done through two 32-bit inboundwindows and two 64-bit inbound windows. All inbound addresses are translated to 40-bitinternal platform addresses.Chapter 25 PCI Express Interface ControllerQorIQ LS1012A Reference Manual, Rev. 1, 01/2018NXP Semiconductors 1413